A Low-Voltage High-Speed DRAM Sense Amplifier Employing Hidden Diode-Connected Offset Cancellation

Abstract

This paper presents a high-speed bit-line sense amplifier (BLSA) designed for low-voltage dynamic random access memory (DRAM). As supply voltages and cell capacitances scale down, BLSA sensing margin is severely degraded by transistor offset and reduced signal levels. While traditional offset-canceling (OC) techniques mitigate these effects, they often introduce additional sensing time. To address this, the proposed architecture utilizes a diode-connected configuration to extract threshold-voltage mismatches, which are subsequently stored in coupling capacitors to compensate offsets. This compensation process is executed simultaneously with charge sharing, effectively hiding the OC timing overhead. Furthermore, a short pre-sensing phase is utilized to enhance the initial sensing margin and accelerate the main sensing operation. Implemented in TSMC 65nm technology, Monte Carlo simulations demonstrate a sensing yield exceeding 99% across a 0.8 V to 1.0 V range. Notably, the design maintains a 100% sensing yield across various process corners and a temperature range of -10°C to 85°C while achieving a fast sensing time of 6.058 ns— which is shorter than those of the compared offset-compensated architectures. With a compact area overhead of 12T+2C, this robust BLSA is highly suitable for sub-1V, low-power memory applications.